#ifndef __RADIX_HEVC_ENC_H__
#define __RADIX_HEVC_ENC_H__
#include "stdint.h"
#include "radix.h"
typedef intptr_t paddr_t;
typedef struct{
  uint8_t roi_en;
  uint8_t roi_md;
  int8_t  roi_qp;
  uint8_t roi_lmbx;
  uint8_t roi_rmbx;
  uint8_t roi_umby;
  uint8_t roi_bmby;
} roi_info_s;

typedef struct _H265E_SliceInfo {
  uint32_t*		des_va;			// vdma descript chain virtual address
  uint32_t*		des_pa;			// vdma descript chain physical address
  uint32_t 		raw_y_pa;		// raw Y base physical address
  uint32_t 		raw_c_pa;		// raw C base physical address
  uint32_t 		dst_y_pa;		// rebuild frame Y physical address
  uint32_t 		dst_c_pa;		// rebuild frame C physical address
  uint32_t 		ref_y_pa;		// reference frame Y physical address
  uint32_t 		ref_c_pa;		// reference frame C physical address
  uint32_t 		bitstream_pa;		// bitstream physical address
  uint8_t 		frame_type;		// 0: B, 1: P, 2: I
  uint8_t 		raw_format;		// 0: NV12, 1: NV21
  uint16_t 		frame_width;		// pixel width of frame
  uint16_t 		frame_height;		// pixel height of frame
  uint16_t		frame_y_stride;		// frame Y stride
  uint16_t 		frame_c_stride;		// frame UV stride
  uint16_t 		dst_y_stride;		// rebuild frame Y stride, default equal to frame_width
  uint16_t 		dst_c_stride;		// rebuild frame C stride, default equal to frame_width
  uint16_t 		ref_y_stride;		// reference frame Y stride, default equal to frame_width
  uint16_t 		ref_c_stride;		// reference frame C stride, default equal to frame_width
  uint8_t 		frame_qp;		// frame start qp;
  int8_t 		frame_cqp_offset;	// chroma QP offset, -12 ~ 12
  uint8_t 		tu_split_en;		// (inter & !2nx2n) tu split ebable
  uint8_t 		time_out_threshold;	// 0-3, time out threshold value

  /* efe parameters */
  uint8_t 		efe_mode;		// default value is 0;
  roi_info_s 		roi_info[16];
  uint8_t 		qpg_max_qp;		// suggest set frame_qp + 13, but not bigger then 51
  uint8_t 		qpg_min_qp;		// suggest set frame_qp - 12, but not less then 0
  uint8_t 		qp_mode;		// 0 - all close, 1 - crp, 2 - sas, 3 - msas, 4 - tab+crp, 5 - tab+sas, 6 - tab+msas
  uint8_t       qpg_cu32_qp_mode;
  uint16_t 		qp_table_len;		// QP table len, not bigger then 1024
  uint8_t       qp_table_en;
  uint32_t*		qp_table;		// QP table virtual address, only for vdma chain.
  uint8_t 		qp_table_cu32_mode;	// CU32 QP select, 0 - first CU16 QP, 1 - average CU16 QP.
  uint16_t 		crp_cu16_threshold[7];
  uint16_t 		crp_cu32_threshold[7];
  int8_t 		crp_cu16_offset[8];
  int8_t 		crp_cu32_offset[8];
  uint8_t 		crp_filter_limit_threshold;
  uint8_t 		crp_filter_top_threshold;
  uint8_t 		crp_filter_left_threshold;
  uint8_t 		crp_filter_right_threshold;
  uint16_t 		sas_cu16_threshold[6];
  uint16_t 		sas_cu32_threshold[6];
  int8_t 		sas_cu16_offset[7];
  int8_t 		sas_cu32_offset[7];

  /* dblk parameters */
  uint8_t 		dblk_en;		// filter is enable
  uint8_t 		sao_en;			// sao is enable
  uint8_t 		sao_y_flag;		// sao y is enable
  uint8_t 		sao_c_flag;		// sao c is enable
  uint8_t 		dblk_gray_en;		// only Y, no UV
  int8_t 		beta_offset_div2;	// -6 ~ +6
  int8_t 		tc_offset_div2;		// -6 ~ +6

  /* bc & sde */
  uint8_t 		use_dqp_flag;		// code dqp enable
  uint8_t 		dqp_max_depth;		// code dqp max depth
  uint8_t 		sign_hide_flag;		// coeff sign hidden enable
  uint8_t 		merge_cand_num;		// mvp cand number
  uint8_t 		context_type; 		// one kind of frame type, used for context model init
  uint8_t       *state;

  /* tfm parameter*/
  uint8_t 		tfm_buf_en;		// bit0:Y8; bit1:Y16; bit2:Y32; bit3:Y64; bit4:C
  uint8_t 		sse_mask;

  /* mce ctrl */
  uint8_t 		inter_mode[4][4]; 	// [depth]: {merge, 2NxN, Nx2N, 2Nx2N}
  uint8_t 		half_pixel_sech_en;
  uint8_t 		quart_pixel_sech_en;
  uint8_t 		refine_cu8_mode;
  uint8_t 		refine_cu16_mode;
  uint8_t 		refine_cu32_mode;
  uint8_t 		mce_scl_mode;

  /* intra mode */
  uint8_t 		ipred_size;		// 7:all 3 channel open 3bit
  uint8_t 		sobel_size;		// 0:all 3 channel open 3bit
  uint8_t 		sobel_en;		// 0:close sobel 1:open sobel
  uint8_t 		md_bc_close;		// 1:close sobel 0:open sobel
  uint8_t 		ppred_slv_dif;		// 0:ppred use ipred_n for ctrl 1:ppred use separate ipx_n for ctrl
  uint8_t 		ppred_mode_num;		// 0:close ppred 1:4mode 2:6mode 3:10mode 3bit
  uint8_t 		ipred_slv_en;		// ipred use slave mode 1bit
  uint8_t 		ppred_slv_en;		// ppred use slave mode only need ppred_n==1  1bit
  uint8_t 		intra_mode[5]; 		// mode4[range2~34] mode3[range0~34] mode2[range0~34] mode1[range0~34] mode0[range0~34]
  uint8_t 		ppred8_mode_num;	// 8x8 0:close ppred 1:4mode 2:6mode 3:10mode 3bit
  uint8_t 		ppred8_slv_en;		// ppred 8x8 use slave mode only need ppred_n==1  1bit
  uint8_t 		intra8_mode[5]; 	// mode4[range2~34] mode3[range0~34] mode2[range0~34] mode1[range0~34] mode0[range0~34]
  uint8_t 		ppred16_mode_num;	// 16x16 0:close ppred 1:4mode 2:6mode 3:10mode 3bit
  uint8_t 		ppred16_slv_en;		// ppred 16x16 use slave mode only need ppred_n==1  1bit
  uint8_t 		intra16_mode[5]; 	// mode4[range2~34] mode3[range0~34] mode2[range0~34] mode1[range0~34] mode0[range0~34]
  uint8_t 		ppred32_mode_num;	// 32x32 0:close ppred 1:4mode 2:6mode 3:10mode 3bit
  uint8_t 		ppred32_slv_en;		// ppred 32x32 use slave mode only need ppred_n==1  1bit
  uint8_t 		intra32_mode[5]; 	// mode4[range2~34] mode3[range0~34] mode2[range0~34] mode1[range0~34] mode0[range0~34]

  /* md ctrl */
  uint8_t 		md_mvs_all;		// value 0xF means all cus' mv sum, value 0 means sum of mv after mode decision
  uint8_t 		md_mvs_abs;		// value 0xF means mv abs sum, value 0 means sum of mv algebraic sum
  uint8_t 		md_pre_pmd[2];		// [0]:low msk, [1]: high msk
  uint8_t 		md_pre_csd[2];		// [0]:cu8, [1]:cu16. value 0:3sse, 1:4sa8d, 2:auto
  uint8_t 		md_force_split;		// force cu split if qps inside are not the same
  uint8_t 		md_pmd_bias[3][2];	// [3]:cu8~32        [2]:enable,value
  uint8_t 		md_csd_bias[4][2];	// [4]:cu8~642       [2]:enable,value
  uint8_t 		md_lambda_bias[3][2];	// [3]:sa8d,sse,stc. [2]:enable,value
  uint8_t 		md_fskip_en; 		// force skip(merge) mode enable
  uint8_t 		md_fskip_cfg;		// force skip(merge) mode configure. 0:reserved, 1:cu64, other:reserved
  uint8_t 		md_fskip_val[8][16];	// [lcuy>>1][lcux>>1]. max 2kx1k

  /* rate ctrl */
  uint8_t 		rc_en;                  // hw ratecontrol enable
  uint8_t 		bu_size;                // lcu numbers in a bu
  uint8_t 		bu_len;                 // bu numbers in a frame
  uint8_t 		rc_method;              // rc alg sel
  uint16_t 		rc_thd[4];              // rc alg threshold
  uint32_t 		rc_info[1024];           // bu's target bits

} _H265E_SliceInfo;

#endif //__RADIX_HEVC_ENC_H__
